1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor device provided with a pad switch for switching electrical connections with respect to a pad.
2. Description of the Related Art
LSIs manufactured at factory are subjected to operation tests at the time of shipment. In the operation tests, a plurality of probe needles of a tester are simultaneously brought in connection with a plurality of pads so as to input required test signals and to detect output signals. Based on the observation of the output signals, a check is made as to whether the operation of the LSI is erroneous.
In order to reduce the costs of the test, it is desirable to shorten the test time by increasing the number of chips that are concurrently tested. In such a case, the number of pads per chip that are connected to the tester is reduced. There is a need to measure an internal power supply voltage by use of a tester in order to check whether the internal power supply voltage generated inside the chip is set to a correct voltage level, or a need to supply an internal power supply voltage directly from an external source for the purpose of setting the internal power supply voltage to a proper voltage level at the time of the test. In such a case, it is desirable to selectively couple a single pad to one of a plurality of internal power supply voltages.
FIG. 1 is a drawing showing an example of a configuration in which pad switches are provided between a pad and a plurality of power supplies (see Patent Document 1 and Patent Document 2, for example).
As shown in FIG. 1, a pad 11 of a semiconductor chip is connected to an internal voltage VREF via a pad switch 12, and is connected to an internal voltage VBB via a pad switch 13. The pad 11 of the semiconductor chip may further be connected to another internal voltage (not shown) via another pad switch (not shown) The internal voltage VREF is a reference potential generated by a reference voltage generator provided inside a semiconductor chip, for example, and the internal voltage VBB is a negative potential generated by a negative potential power supply unit provided inside the semiconductor chip, for example.
The pad switch 12 becomes conductive (i.e., establishes an electrical path) in response to the asserted state (e.g., HIGH) of a test signal tes1 so as to electrically connect the pad 11 to the internal voltage VREF. By the same token, the pad switch 13 becomes conductive (i.e., establishes an electrical path) in response to the asserted state (e.g., HIGH) of a test signal tes2 so as to electrically connect the pad 11 to the internal voltage VBB.
FIG. 2 is a drawing showing an example of the circuit configuration of the pad switch. The pad switch 12 shown in FIG. 2 includes an NMOS transistor 15, a PMOS transistor 16, and an inverter 17. The test signal tes1 is applied to the gate of the NMOS transistor 15, and an inversion of the test signal tes1 is applied to the gate of the PMOS transistor 16 via the inverter 17.
The substrate potential (back-gate potential) of the NMOS transistor 15 is set to the lowest potential among the power supply voltages that are output to the pad 11. In this example, the internal voltage VBB is output to the pad 11 as shown in FIG. 1, so that the substrate potential of the NMOS transistor 15 is set to VBB. This arrangement prevents the diffusion layer junction to be placed in the forward-direction biased state when the pad 11 is set to VBB.
The substrate potential (back-gate potential) of the PMOS transistor 16 is set to the highest potential among the power supply voltages that are output to the pad 11. In this example, taking into account a situation in which the power supply voltage VDD is output to the pad 11, the substrate potential of the PMOS transistor 16 is set to VDD. This arrangement prevents the diffusion layer junction to be placed in the forward-direction biased state when the pad 11 is set to VDD.
FIG. 3 is a drawing for explaining operations performed when electrical connections between the pad 11 and the internal power supply voltages are switched in response to the test signals. When a voltage is applied to the interior of the semiconductor chip via the pad 11, there is a need to prevent short-circuiting between power supply units and the application of an unintended voltage. To this end, the test signals are switched so as to provide a period during which all the pad switches are OFF as shown in FIG. 3, and the voltage applied from the external source is changed during this period.
Even if the configuration of FIG. 2 and the operations of FIG. 3 are used, however, there is still a problem in that the pad switches cannot be placed in the OFF state when a voltage exceeding the internal power supply voltage (i.e., the power supply voltage used inside the chip) is applied. In the following, a description will be given of an example in which a voltage (e.g., −2.0 V) lower than the internal negative-potential power supply voltage VBB (e.g., −0.5 V) is applied to the pad 11 from an external source. In the configuration shown in FIG. 1, a voltage of −2.0 V may be applied to the pad 11 from an external source, so that the voltage equal to −2.0 V is supplied from the pad 11 to the interior of the chip via another pad switch (not shown). In such a case, the NMOS transistor 15 and the PMOS transistor 16 (see FIG. 2) of the pad switch 12, for example,. need to be placed in the nonconductive state (OFF state).
FIG. 4 is a drawing for explaining the operation of the NMOS transistor 15 shown in FIG. 2 when a voltage lower than the internal voltage VBB is applied from an external source to the pad 11.
When the NMOS transistor 15 is to be set to the OFF state, the test signal applied to the gate node of the NMOS transistor 15 is VBB. The voltage applied to the back gate node is also VBB, as previously described. The pad 11 and the internal power supply VREF are connected to the source node and the drain node, respectively.
When the voltage of the pad 11 is lower than the internal negative-potential power supply voltage VBB, the N-type diffusion layer junction of the NMOS transistor 15 is placed in the forward-bias state, so that the voltage VBB of the back gate node is set to the voltage that is the pad voltage (i.e., the voltage of the source node) plus the forward voltage (Vf) that is approximately 0.6 V. As a consequence, the voltage VBB applied to the gate node is changed to the voltage that is higher than the source voltage only by Vf, resulting in the NMOS transistor 15 being not in the OFF state. Namely, the NMOS transistor 15 becomes conductive, and, thus, the internal voltage VREF is coupled to the pad 11.
What is described above is directed to the state of the NMOS transistor when a voltage lower than the internal negative-potential power supply voltage is applied to the pad 11. In the same manner, the state of the PMOS transistor 16 undergoes a similar process, and the OFF state is lost, when a voltage higher than an internal stepped-up power supply voltage is applied to the pad 11.
Further, there is a problem in that the conductance of the NMOS transistor 15 becomes small when the potential VREF (e.g, 1.0 V) situated approximately in the middle between VDD (1.6 V) and VBB (−0.5 V) is coupled to the pad 11. FIG. 5 is a drawing for explaining the operation of the NMOS transistor 15 shown in FIG. 2 when the pad 11 is set to the voltage VREF.
When the NMOS transistor 15 is to be set to the ON state, the test signal applied to the gate node of the NMOS transistor 15 is VDD (1.6 V). The voltage applied to the back gate node is VBB (−0.5 V), as previously described. The source node and drain node are set to the internal power supply voltage VREF (1.0 V).
In this case, a voltage Vbs between the back gate and the source becomes as large as −1.5 V due to the setting of the source node to the middle potential, resulting in the threshold voltage (Vth) rising due to the back-bias effect. Also, a gate-source voltage Vgs becomes as small as 0.6 V. As a result, the conductance of the NMOS transistor 15 is lowered, giving rise to the problem that electrical conductance is not sufficient.
[Patent Document 1] Japanese Patent Application Publication No. 63-257242
[Patent Document 2] Japanese Patent Application Publication No. 8-304515
[Patent Document 3] Japanese Patent Application, Publication No. 4-22000
Accordingly, there is a need for a pad switch that can maintain its OFF state even when a voltage higher than the internally used power supply voltage is applied to the pad, and that can assume a sufficient ON state even when a middle potential couples between an internal power supply and the pad.